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Capturing a first digital signal

Objectives

Section titled “Objectives”

By the end of this lesson you will:

  1. Connect a logic analyzer’s ground and signal leads to a board correctly
  2. Choose a sample rate fast enough for the signal you want to measure, and explain what happens when it is too slow
  3. Measure a blink signal’s pulse width and frequency from a capture

Before you start

Section titled “Before you start”
  • An inexpensive logic analyzer that works with sigrok (many models use the fx2lafw driver), with leads and clips
  • PulseView installed on your computer — plug the device in and check that the program can see it
  • A TESAIoT Dev Kit flashed with the QWA309 Header I/O Test example, which generates a signal for us to measure on the header
  • If using the Eva Kit, write a program that blinks a spare pin at a rhythm you know, e.g. 250 ms on, 250 ms off, and measure that pin instead

Instrument safety. Most inexpensive logic analyzers have no ground isolation — their ground is your computer’s ground. Never connect one to a circuit whose ground is not the same as your computer’s, or to a circuit carrying mains power, and always check the device’s maximum input voltage spec before use.

See it work first

Section titled “See it work first”

Run the header test program and press the PWM Out button. The screen states it is driving P13.3 and P13.4 as a phase-inverted pair, for 50 cycles, half-period 20 ms, “approximately 25 Hz.” If you have an LED with a 1 kΩ resistor wired to pin P13.3 (as in the lesson Basic components), you will see it blink so fast it almost looks solidly lit, for about two seconds.

Your eyes can only tell you “it blinks fast” — they cannot answer whether it is really 25 Hz, whether every pulse is the same width, or whether all 50 cycles actually happened. A multimeter cannot answer either, because it averages the value. The instrument that can answer is a logic analyzer.

Concepts

Section titled “Concepts”

1. How a logic analyzer works, and how to connect it

Section titled “1. How a logic analyzer works, and how to connect it”

A logic analyzer reads each channel’s voltage at a fixed rhythm, compares it against a threshold, and stores it as 0 or 1 in time order. The program on your computer draws the result as a square waveform. It has no idea what the real voltage is — only whether it is above or below the threshold (to see the real voltage, you need an oscilloscope, in Module 5).

Ground first, always. Voltage is the difference between two points. A logic analyzer’s signal channels measure relative to its own GND lead. If GND is not connected to the board’s GND, the instrument has no reference point, and the result will be garbage or a flat line, even if the signal lead is connected correctly. The right order is: connect GND → connect the signal lead → open the program, and disconnect in reverse.

Voltage levels must match. Check the spec to confirm the instrument’s input threshold can read a 3.3 V signal (almost every model can). For 1.8 V signals, some models can read them, while others sit close enough to the threshold to be unreliable.

Choosing which pin to probe. Probe or clip only header pins or test points, using a clip designed to grip a pin. Never let a bare metal lead tip touch a neighbouring pin.

2. Sample rate, and when it is too slow

Section titled “2. Sample rate, and when it is too slow”

The sample rate (f_s) is how many times per second the device reads. The gap between two samples is T_s = 1 / f_s, which is the time resolution you can measure with. An edge that happens between two samples will only be seen at the next sample, so a measured pulse width can be off by about one T_s.

How fast is fast enough? The Nyquist–Shannon sampling theorem says a signal with maximum frequency f must be sampled faster than 2f to be reconstructed. But timing a digital signal needs more than that. A common rule of thumb is at least 4 samples across the narrowest pulse, and 10 or more samples if you want to time it accurately.

Signal Narrowest interval Suitable sample rate
The header test program’s 25 Hz PWM 20 ms 10 kHz is already enough (0.1 ms resolution, or 0.25% of the 40 ms period)
UART at 115200 baud 1 bit = 1 / 115200 = 8.68 µs 1 MHz gives 8.7 samples per bit; 4 MHz is more comfortable
I2C at 400 kHz SCL’s high or low half is about 1.25 µs 4 to 10 MHz

If it is too slow, two symptoms appear.

  • Missing pulses. A pulse narrower than T_s can fall entirely between two samples, and the device never sees it at all.
  • Aliasing. A fast signal, sampled too slowly, looks like a slower signal that does not really exist.
signal on the wire (fast) what a too-slow sample rate shows (a slower, wrong signal)
Top: the real signal on the wire, with dots marking each sample. Bottom: the picture the device draws from those dots — its frequency is wrong. This is aliasing.

Example: a 1 kHz square wave is sampled at 1.1 kHz. Each sample lands 1000 / 1100 = 0.909 cycles further along the wave — equivalent to slipping backward by 0.091 cycles each time. The result completes one full cycle every 11 samples, giving 1100 / 11 = 100 Hz. This false frequency equals |1100 − 1000| Hz. The picture looks clean and convincing — this is exactly why aliasing is dangerous. It never looks like a mistake.

Memory. Number of samples = f_s × capture time. Sampling at 1 MHz for 5 s gives 5 million samples per channel. Setting the rate higher than necessary wastes memory and shortens how long you can capture. A device that streams over USB continuously may not sustain its top rate when many channels are enabled at once.

3. Trigger, and timing measurements

Section titled “3. Trigger, and timing measurements”

A trigger is a condition that tells the device “start capturing here” — for example, a rising edge on channel 0. The device waits until the condition is true, then captures samples around that point. This means you never have to press start in time for the event, and the event lands in the same position every time you capture.

Measuring time from a capture. Use the program’s time-measurement tool (cursors or markers), placed on the signal’s edges.

Pulse width (t_high)  = the falling edge's time − the previous rising edge's time
Period (T)             = the next rising edge's time − the first rising edge's time
Frequency (f)           = 1 / T
Duty cycle              = t_high / T

Measuring several periods and dividing by the count is more accurate than measuring a single period, because the roughly one-T_s error at each edge also gets divided by the number of periods.

Worked example

Section titled “Worked example”

Problem: capture the signal from the header test program’s PWM Out button, then measure its frequency, pulse width, and count its cycles.

  1. Know what to expect first. From the on-screen description, the half-period is 20 ms, so the period is about 40 ms, frequency about 25 Hz, duty about 50%, for 50 cycles, lasting about 2 s total. P13.4 should be phase-inverted from P13.3 the whole time.
  2. Connect the leads. The device’s GND to the header’s GND, channel 0 to P13.3, channel 1 to P13.4.
  3. Choose a sample rate. The narrowest interval is 20 ms; at 10 kHz, that gives 200 samples across it — 0.1 ms resolution, more than enough.
  4. Choose a capture time. At least 3 s, to cover the signal’s 2 s, giving 10 kHz × 3 s = 30,000 samples per channel.
  5. Set the trigger to channel 0’s rising edge. Press Run in the program, then press PWM Out on screen.
  6. Measure (the following numbers are sample data). The first rising edge is at 0 ms; the 11th rising edge is at 401.0 ms. Average period = 401.0 / 10 = 40.10 ms. Frequency = 1 / 40.10 ms = 24.94 Hz. The first pulse’s width is 20.05 ms; duty = 20.05 / 40.10 = 50.0%.
  7. Interpret. The period is 0.1 ms (0.25%) longer than 40 ms, because the program generates the signal by writing the pin and delaying in software — every cycle picks up a small extra amount of time from other instructions. If your device’s 0.1 ms resolution is too coarse to tell this difference apart, raise the sample rate to 100 kHz and measure again.
  8. Count the cycles. Use a decoder, or count rising edges — you must get exactly 50 edges, and channels 0 and 1 must never both be 1 at the same time, anywhere.

Practice

Section titled “Practice”
  1. To capture UART at 115200 baud with at least 8 samples per bit, what sample rate do you need at minimum?
  2. Sampling at 1 MHz for 5 s, using 8 channels — how many samples per channel does the device need to store, and how many in total?
  3. A 900 Hz square wave is sampled at 1 kHz. What frequency will you see in the result?
  4. In a capture, rising edges are at 12.0 ms and 52.1 ms, with a falling edge between them at 32.0 ms. Find the period, frequency, pulse width, and duty cycle.
  5. A signal has a pulse 3 µs wide, sampled at 200 kHz. What happens? What should you change it to?
  6. If you forget to connect the logic analyzer’s GND lead, what would the result probably look like, and why?

Solution

Section titled “Solution”
  1. 115200 × 8 = 921,600 samples per second — use 1 MHz (giving 8.7 samples per bit)
  2. 1 MHz × 5 s = 5 million samples per channel; across 8 channels, 40 million total
  3. |1000 − 900| = 100 Hz
  4. Period = 52.1 − 12.0 = 40.1 ms. Frequency = 1 / 40.1 ms = 24.9 Hz. Pulse width = 32.0 − 12.0 = 20.0 ms. Duty = 20.0 / 40.1 = 49.9%.
  5. The 5 µs gap between samples is wider than the 3 µs pulse — the pulse might vanish entirely, or show as just a single sample. You need at least 4 samples per pulse, i.e. 4 / 3 µs ≈ 1.33 MHz; choose 2 MHz or higher (10 samples per pulse would use about 4 MHz).
  6. The result would be garbage, or a flat, unchanging line, or something that shifts as you move the wire — because the signal channel has no shared reference point with the board, so the voltage the device sees is not the signal’s voltage relative to the board’s GND.

Check your understanding

Section titled “Check your understanding”

Answer at least 4 of the 5 questions in quiz.yaml correctly.

Lab

Section titled “Lab”

Part A: a slow blinking signal (GPIO Out)

  1. Connect the device’s GND to the header’s GND, then connect channels 0 through 5 to P13.0, P13.3, P13.4, P13.5, P13.6, P13.7 in order (if your device has fewer channels, use just the first two pins).
  2. Set the sample rate to 10 kHz, capture time 20 s, and trigger on channel 0’s rising edge.
  3. Press Run, then press GPIO Out on screen. The program drives each pin to 1 in turn, about 0.7 s each, in sequence, then turns everything off — repeated three times.
  4. Guess before looking at the result: will each pin’s pulse width be longer than 700 ms, or shorter, and why? (Hint: look at the example’s code for what runs between the two delay calls.)
  5. Measure channel 0’s pulse width across all three rounds, and the time from channel 0’s rising edge to channel 1’s rising edge. Record it in the table.

Part B: a faster signal (PWM Out)

  1. Connect channel 0 to P13.3 and channel 1 to P13.4. Follow the worked example, measure the average period across 10 periods, the frequency, the pulse width, and count the cycles.
  2. Deliberately make it too slow. Lower the sample rate to the lowest your device allows, and capture again. If your device is still too fast to show an effect on a 25 Hz signal, calculate instead at what sample rate the problem would start to show, and what you would see.
  3. Try PulseView’s Timing decoder (if your version has it), which shows the time between edges automatically — compare it against your own manual measurement.
Measurement Expected Measured
P13.0’s pulse width (GPIO Out) about 0.7 s
Rising edge of P13.0 to rising edge of P13.3 about 0.7 s
Average period across 10 periods (PWM Out) about 40 ms
Frequency about 25 Hz
P13.3’s duty cycle about 50%
Number of cycles 50
Any interval where P13.3 and P13.4 are both 1? none

Going further

Section titled “Going further”

The next lesson, Decoding I2C and UART, has the program read a signal’s meaning for us — from a device’s address on the I2C bus, to the bytes travelling on a UART wire.

Reflect

Section titled “Reflect”

In Part A, did you guess correctly whether the pulse would be longer or shorter than 700 ms? What does this tell you about generating timing with software delays?

References

Section titled “References”

Review questions

Answer on your own first, then open the answer.

  1. The logic analyzer's signal lead is on a board pin, but its GND lead is not connected. What is the likely result? (Objective 1)

    1. ภาพถูกต้องตามปกติ เพราะ USB ต่อกราวด์ให้เองเสมอ
    2. ภาพมั่ว เป็นเส้นคงที่ หรือเปลี่ยนเมื่อขยับสาย เพราะเครื่องไม่มีจุดอ้างอิงร่วมกับบอร์ด
    3. บอร์ดจะรีเซ็ต
    4. เครื่องจะวัดแรงดันจริงได้แทนค่า 0 และ 1
    Show answer

    Answer: B. ภาพมั่ว เป็นเส้นคงที่ หรือเปลี่ยนเมื่อขยับสาย เพราะเครื่องไม่มีจุดอ้างอิงร่วมกับบอร์ด

    ช่องสัญญาณวัดแรงดันเทียบกับ GND ของเครื่อง ถ้าไม่มีสาย GND ร่วมกับบอร์ด ไม่มีอะไรรับประกันว่าจุดอ้างอิงสองฝั่งเท่ากัน ต่อ GND ก่อนสายสัญญาณทุกครั้ง

  2. Which order is best for connecting a logic analyzer to a board? (Objective 1)

    1. ต่อสายสัญญาณก่อน แล้วต่อ GND ทีหลังถ้าภาพไม่นิ่ง
    2. ต่อ GND ก่อน แล้วต่อสายสัญญาณ แล้วจึงเริ่มจับ
    3. ไม่ต้องต่อ GND ถ้าบอร์ดใช้ไฟจาก USB
    4. ต่อสายสัญญาณเข้าขาชิปโดยตรงให้ใกล้ที่สุด
    Show answer

    Answer: B. ต่อ GND ก่อน แล้วต่อสายสัญญาณ แล้วจึงเริ่มจับ

    ต่อจุดอ้างอิงก่อนเสมอ แล้วหนีบสายสัญญาณที่ขา header หรือจุดทดสอบ การจิ้มขาชิปที่ถี่เสี่ยงลัดวงจรขาข้าง ๆ

  3. You need at least 8 samples per bit on a 115200 baud UART. Which is the lowest sample rate that works? (Objective 2)

    1. 115.2 kHz
    2. 230.4 kHz
    3. 500 kHz
    4. 1 MHz
    Show answer

    Answer: D. 1 MHz

    115200 × 8 = 921.6 kHz ในตัวเลือกมีเพียง 1 MHz ที่เกินค่านี้ (ได้ราว 8.7 ตัวอย่างต่อบิต)

  4. A 1 kHz square wave is sampled at 1.1 kHz. What frequency does the capture show? (Objective 2)

    1. 1 kHz
    2. 1.1 kHz
    3. 100 Hz
    4. 2.1 kHz
    Show answer

    Answer: C. 100 Hz

    สุ่มช้ากว่า 2 เท่าของความถี่สัญญาณมาก เกิด aliasing ความถี่ปลอมคือ |1100 − 1000| = 100 Hz และภาพดูสะอาดน่าเชื่อ จึงอันตราย

  5. Rising edges at 5.0 ms and 25.0 ms, with a falling edge at 10.0 ms between them. What are the frequency and duty cycle? (Objective 3)

    1. 50 Hz และ 25%
    2. 40 Hz และ 25%
    3. 50 Hz และ 75%
    4. 200 Hz และ 50%
    Show answer

    Answer: A. 50 Hz และ 25%

    คาบเวลา 25.0 − 5.0 = 20 ms จึงได้ 50 Hz ความกว้างพัลส์ 10.0 − 5.0 = 5 ms duty = 5 / 20 = 25%

Cite this lesson

If you teach from this lesson or reuse it in slides or documents, credit it with the text below. If you changed it, add (adapted) after the title.

"Capturing a first digital signal" from TESA Open Knowledge by the Thai Embedded Systems Association (TESA), https://github.com/tesaiot/tesa-qualification-program, licensed under CC BY-NC 4.0

Thai attribution: "จับสัญญาณดิจิทัลครั้งแรก" จาก TESA Open Knowledge โดยสมาคมสมองกลฝังตัวไทย (Thai Embedded Systems Association: TESA) https://github.com/tesaiot/tesa-qualification-program สัญญาอนุญาต CC BY-NC 4.0

Lesson link: https://tesaiot.github.io/tesa-qualification-program/en/courses/electronics-and-instruments/m04-logic-analyzer/l01-capture-a-signal/

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TESA Open Knowledge · © 2026 สมาคมสมองกลฝังตัวไทย (TESA) · CC BY-NC 4.0

Content is licensed CC BY-NC 4.0. Reuse it non-commercially and credit the Thai Embedded Systems Association (TESA) every time. · How to cite TESA